一种混合结构高速LDPC编码器的FPGA实现  

Implementation of High-Speed Mix-Architecture LDPC Encoder in FPGA

作　　者：贺刚[1] 柏鹏[1] 彭卫东[1] 王明芳[2] 李明阳[1] 赵学军[1] 高升强 

机构地区：[1]空军工程大学科研部信息中心,西安710051 [2]空军工程大学导弹学院,陕西三原713800 [3]西安陆军学院,西安710108

出　　处：《微电子学》2012年第3期398-401,405,共5页Microelectronics

基　　金：国家"973"计划基金资助项目(2009CB613306)

摘　　要：分析了准循环低密度奇偶校验码生成矩阵的结构特点,讨论了硬件可实现的三种常见编码器结构,提出了一种混合结构的FPGA实现方法。通过利用循环矩阵的结构特性,增加少量硬件开销,就可以实现编码器高速编码,满足高速通信需求,吞吐量达1.36Gb/s。Structural characteristics of QC-LDPC code generation matrix were analyzed, and three popular strut tures for hardware encoder were discussed. A mix-architecture was proposed for implementation of encoder in FP GA. In this design, high speed encoding with a throughput up to 1.36 Gb/s could be achieved by taking advantages of circulate matrix and adding some hardware resource, to satisfy the demand of high-speed communications.

关 键 词：LDPC编码器 FPGA 混合结构 准循环LDPC码 

分 类 号：TN911.22[电子电信—通信与信息系统]