FPU加法器的设计与实现  

Design and implementation of floating-point adders

作　　者：田祎[1] 颜军[1] 

机构地区：[1]商洛学院计算机科学系,陕西商洛726000

出　　处：《电子设计工程》2012年第12期13-15,20,共4页Electronic Design Engineering

基　　金：商洛学院科研基金项目(09SKY004)

摘　　要：浮点运算器的核心运算部件是浮点加法器,它是实现浮点指令各种运算的基础,其设计优化对于提高浮点运算的速度和精度相当关键。文章从浮点加法器算法和电路实现的角度给出设计方法,通过VHDL语言在QuartusII中进行设计和验证,此加法器通过状态机控制运算,有效地降低了功耗,提高了速度,改善了性能。Floating point adders is the core component of FPU, It＇s the foundation of floating-point operation instruction, To improve the design optimization is very important of floating-point calculation speed and precision. This article from the floating-point adder algorithm and circuit implementation give design method, Through the VHDL language in Quartusii in design and validation ,The adder through the FSM control operations, Effective to reduce the power consumption, Improve the speed and function.

关 键 词：浮点运算 加法器 设计 VHDL 状态机 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]