Gardner定时同步环路参数设计及性能分析  

Parameters design and performance analysis of the timing recovery loop based on Gardner timing detector

作　　者：付永明[1] 朱江[1] 琚瑛珏[1,2] 

机构地区：[1]国防科学技术大学电子科学与工程学院 [2]解放军61062部队

出　　处：《通信学报》2012年第6期191-198,共8页Journal on Communications

摘　　要：以数字锁相环理论为依据,对Gardner定时误差检测器反馈定时环路参数的设计进行了深入研究,基于MATLAB对一阶、二阶环路性能进行了仿真,重点分析了环路阶数和等效噪声带宽对系统性能的影响,得到了等效噪声带宽与定时同步环路性能的关系,为定时同步环路的设计提供了理论依据。In-depth research was carried out into parameters design in the feedback timing recovery loop based on Gardner timing error detector,according to the theory of digital phase-lock loop.MATLAB based simulation was performed for both first-order and second-order loop.Comprehensive analysis of the influence from loop order and noise-equivalent bandwidth on synchronization performance indicates the relationship between synchronization performance and noise-equivalent bandwidth,which provides a theoretic reference for timing recovery loop design.

关 键 词：定时同步 Gardner定时误差检测器 数字锁相环 环路参数 同步性能 

分 类 号：TN911[电子电信—通信与信息系统]