GaAs衬底制备40nmT型栅工艺  

40nm T-gate Preparation Technology on GaAs Substrate

作　　者：刘帆[1,2] 苑进社[1] 时文华[2] 

机构地区：[1]重庆师范大学物理与电子工程学院,重庆400047 [2]中国科学院苏州纳米技术与纳米仿生研究所,苏州215123

出　　处：《重庆理工大学学报（自然科学）》2012年第6期95-97,共3页Journal of Chongqing University of Technology：Natural Science

基　　金：国家自然科学基金资助项目(10990102)

摘　　要：采用双层胶工艺电子束光刻在GaAs衬底上制备40 nm栅长T型栅。制备过程仅需1次曝光1次显影,使得工艺制备过程得到简化;优化的栅制作工艺保证了形貌良好的栅线条。实验结果表明,该方法能制备40 nm栅长的T型栅,基本满足器件制作要求。New advances in e-beam lithography have made possible the fabrication of HEMT with gate length well in the nanometer regime. Double layers resist technology with electron beam lithography on a GaAs substrate is used to prepare 40nm gate length T-gate . This method requires only one lithogra- phy and one development, which can be applied to simplify the process and get a narrower gate. The ratio of head to footprint of the T gate is controllable. The experiment results show that the way meets the need of the device fabrication.

关 键 词：T型栅 双层胶 1次曝光1次显影 

分 类 号：TM23[一般工业技术—材料科学与工程]