IDEA算法高速密钥生成模块的FPGA实现  

High Performance Keys Generator of IDEA for FPGA Implementation

作　　者：唐朝伟[1] 庄严[1,2] 王恒[1] 

机构地区：[1]重庆大学通信工程学院,重庆400044 [2]96212部队,广东515300

出　　处：《世界科技研究与发展》2012年第3期414-418,共5页World Sci-Tech R&D

摘　　要：提出了一种基于FPGA的高速IDEA算法密钥生成方案。详细介绍了IDEA密钥生成模块的子模块的功能划分、设计实现及性能分析,对直接影响速度性能的模乘和模乘逆运算,提出改进的硬件实现结构。在此基础上,设计了新的IDEA密钥生成模块FPGA实现方案以克服其常用结构所存在的缺陷。仿真结果表明,其速度性能有了较大的提高,且该结构能在速度与资源消耗之间取得一个较好的平衡。A high performance keys generator of IDEA is presented based on FPGA. Detailed description is given to the division and the de- sign of the sub-function modules of IDEA keys generator, which the time and logic resources consumption analysis of these modules are showed. Modified architectures for both modulo multiplier and inverse modulo multiplier are put forward,which have direct influence on the performance of the speed. On the basis of these, a new structure of IDEA keys generator for FPGA implementation is proposed to overcome the flaw of the common. Results from simulation show that the dedicated structure achieves a higher speed than before. And it is a good trade-off between speed and resources consumption.

关 键 词：国际数据加密算法 密钥生成 模乘 模乘逆 现场可编程门阵列 

分 类 号：TN918.4[电子电信—通信与信息系统]