低功耗并行LTE-Turbo译码器的VLSI结构设计及实现  

Low Power Parallel VLSI Architecture for LTE Turbo Decoder

作　　者：李晓峰[1] 冯大政[1] 胡树楷[2] 

机构地区：[1]西安电子科技大学雷达信号处理国家重点实验室,西安710071 [2]西安电子科技大学综合业务网理论及关键技术国家重点实验室,西安710071

出　　处：《计算机辅助设计与图形学学报》2012年第7期968-974,共7页Journal of Computer-Aided Design & Computer Graphics

基　　金：国家自然科学基金(60971111);国家"九七三"重点基础研究发展计划项目(2010CB328300)

摘　　要：针对3GPP LTE标准中的Turbo码,设计了一种基于最大后验概率算法的低功耗并行译码器.根据二次置换多项式交织器的整数数学特性,分解并行处理中每个译码器的交织地址为子码块地址和块内偏移地址,提出一种高效的递归计算子码块交织地址的算法,使得并行度可以为任意值,而不仅仅限于2的幂次;并依此设计了低复杂度的实时递归计算交织器的互连结构,以避免传统实现方法中对交织地址的存储,有效地简化了Turbo译码器本征信息处理的互连网络,减小了实现面积和功耗;最后从结构级进行优化设计,进一步减少面积和功耗.实验结果表明,在40nm的工艺下,约束工作电压为1.18V、时钟频率为282MHz,版图实现可以达到130Mb/s的吞吐量,且功耗仅为107mW,每次迭代能量效率为0.107nJ/bit.Targeted to 3GPP LET standard, this paper proposes a parallell-structured turbo decoder in low power consumption based on the maximum a-posteriori algorithm. Taking advantage of the mathmetical property of the quadratic permutation polynomial, the address of each interleaver, in the parallel processing structure, is separated into two parts, block address and offset address in that block. An recursive algorithm is developed to calculate these two addresses in a parallel decoder, which leads to the parallelism can be any value, breaking the limitation of the power of 2. Relying on the developed algorithm a reeursive VLSI architecture is presented, which significantly simplifies the extrinsic information interconnecting networks and avoids the usage of interleaver storage memory in the conventional approach, and remarkably decreass the power and area. Architecture level optimization strategies are also explored to further reduce the VLSI area and power consumption. Implemented with 40 nm technology, 1.18 V power supply and 283 MHz clock, post-layout shows that the decoder achieves 130 Mb/s throughout at 107 mW power consumption and 0. 107 nJ/hit/iteration in energy efficiency.

关 键 词：TURBO码 最大后验概率译码器 二次置换多项式交织器 超大规模集成电路 

分 类 号：TN47[电子电信—微电子学与固体电子学]