基于NiosⅡ的智能多接口片上系统设计  

Design of a multi-interface SoC based on NiosⅡ

作　　者：张兴堂[1] 高勇 王伟强[1] 

机构地区：[1]江苏自动化研究所,江苏连云港222006 [2]空军驻扬州地区军代室,江苏扬州225000

出　　处：《电子技术应用》2012年第7期61-64,共4页Application of Electronic Technique

摘　　要：设计了一种基于NiosⅡ处理器的片上系统(SoC),集成了NiosⅡ处理器IP、PCI接口IP、网络接口IP以及基于Wishbone总线的串行接口IP核、CAN接口IP核等。系统具有可重配置、可扩展、灵活、兼容性高、功耗低等优点,适合于片上系统开发与应用。本设计使用Verilog HDL硬件描述语言在QuartusⅡ环境下进行IP软核设计、综合、布局布线,在Model Sim下完成功能、时序仿真,在SoPC下完成系统的定制与集成,在NiosⅡ IDE环境下完成片上系统软件程序的开发,最后在FPGA器件上实现了智能多接口功能的片上系统。This paper analyses the design of a SoC based on NiosII,that composed of the NiosII Processor and the Interface of PCI,Network,UART and CAN that based on Wishbone bus. The SoC has the advantages of flexibility, configurability, opening, ex- tending, smallness and low consuming. So it is ideal for the research and develop of SoC. Verilog hardware description language in the Quartus II environment has been used for its design, compilation and simulation. The multi-interface SoC based on NioslI has been implemented using FPGA technology in the SoPC environment of Nios II IDE.

关 键 词：FPGA NIOSII 片上系统 IP核 

分 类 号：TN47[电子电信—微电子学与固体电子学]