4nm超薄栅nMOSFET中漏电压对栅控产生电流影响研究  

Effect of Drain Voltage on the Gate-controlled Generation Current in 4nm-gate-oxide LDD nMOSFT＇s

作　　者：陈海峰[1] 过立新[1] 商世广[1] 

机构地区：[1]西安邮电学院电子工程学院,陕西西安710121

出　　处：《纳米科技》2012年第3期23-26,共4页

基　　金：陕西省教育厅专项科研基金（编号：1IJK0902）,西安市应用材料创新基金（编号：XA-AM-201012）,西安邮电学院青年教师科研基金f编号：ZL2010-19）

摘　　要：研究了90nmCMOS工艺下4nm超薄栅氧化层LDDnMOSFET中漏电压VD对栅调制产生电流‰的影响，随着VD的增加，IGD曲线上升沿不变，而下降沿向右漂移，这归因于VD增大引发了闽值电压增大所致。研究发现IGD下降沿最大跨导GMW随着VD的变化成幂指数关系：GMW=VDn，n=0．08。进一步发现电流上升沿与下降沿最大跨导所对应的栅电压VG差与VD成线性关系，斜率为1．19。文中给出了相关的物理机制。The effect of drain voltage VD on the gate-controlled generation current IGD has been investigated in 4nm- gate-oxide LDD nMOSFET fabricated by 90nm CMOS process. It is found that the rising edge of IGD curve keeps no- change and the falling edge of that shifts rigbtwards as increasing VD. This is because that the increase of Vt） results in an increase in VTH. The maximum transconductance of IGD＇s falling edge （GMw） has the power function relationship with VD-： GMW=VDn, n=0.08. Further, the difference of Vc at the maximum transconductanee of the IGD＇s falling and rising edges has the linear relationship with VD and the slope is 1.19. The related mechanisms were given in the paper.

关 键 词：栅氧化层 漏电压 闽值电压 浅掺杂漏区 

分 类 号：TN386.1[电子电信—物理电子学]