基于多值逻辑的8位条件和加法器  

A 8 bit Conditional Sum Adder Based on Multiple-Valued Logic

作　　者：吴海霞[1] 屈晓楠[1] 赵显利[1] 仲顺安[1] 夏乾斌[1] 

机构地区：[1]北京理工大学信息与电子学院,北京100081

出　　处：《北京理工大学学报》2012年第6期607-610,616,共5页Transactions of Beijing Institute of Technology

基　　金：北京理工大学基础研究基金项目(3050012211106);北京理工大学大学生创新项目(101000718)

摘　　要：针对改善算术VLSI系统的性能,提出了一种基于四值逻辑的加法器设计.采用源极耦合动态多值电流模电路,利用条件和算法,设计实现了基于四值逻辑的8-bit加法器.利用HSPICE软件,在0.18μm CMOS工艺下,电源电压为1.8V,时钟频率为100MHz的条件下,进行了仿真.仿真结果表明,所设计的加法器平均功耗为2.8mW,高位和的平均延迟为0.689ns,高位进位的平均延时是0.452ns,所用晶体管数是636.To improve the performance of arithmetic VLSI system, a kind of multiple-valued current-mode （MVCM） circuitry based on dynamic source-coupled logic is presented. With the circuitry, a design of the 4-quatrit quaternary adder is designed based on conditional sum addition, which implements 8-bit addition operation. The calculation speed of VLSI is improved by the use of conditional sum logic. The designed adder is evaluated by HSPICE simulation in a 0. 18μm CMOS technology with the supply voltage of 1.8 V. The results show that its power dissipation is about 2.8 mW, the delay of sum and carry is 0. 689 ns and 0. 452 ns respectively, and the transistor counts is 636.

关 键 词：多值逻辑 多值电流模 条件和加法运算 

分 类 号：TN453[电子电信—微电子学与固体电子学]