A low on-resistance triple RESURF SOI LDMOS with planar and trench gate integration  

作　　者：罗小蓉 姚国亮 张正元 蒋永恒 周坤 王沛 王元刚 雷天飞 张云轩 魏杰 

机构地区：[1]State Key Laboratory of Electronic Thin Films and Integrated Devices.University of Electronic Science and Technology of China [2]No.24 Research Institute of China Electronics Technology Group Corporation

出　　处：《Chinese Physics B》2012年第6期560-564,共5页中国物理B（英文版）

基　　金：Project supported by the National Natural Science Foundation of China (Grant Nos. 61176069 and 609 76060);the National Key Laboratory of Analogue Integrated Circuit (Grant No. 9140C090304110C0905)

摘　　要：A low on-resistance （Ron,sp） integrable silicon-on-insulator （SOI） n-channel lateral double-diffused metal-oxide-semiconductor （LDMOS） is proposed and its mechanism is investigated by simulation. The LDMOS has two features： the integration of a planar gate and an extended trench gate （double gates （DGs））; and a buried P-layer in the N-drift region, which forms a triple reduced surface field （RESURF） （TR） structure. The triple RESURF not only modulates the electric field distribution, but also increases N-drift doping, resulting in a reduced specific on-resistance （Ron,sp） and an improved breakdown voltage （BV） in the off-state. The DGs form dual conduction channels and, moreover, the extended trench gate widens the vertical conduction area, both of which further reduce the Ron,sp. The BV and Ron,sp are 328 V and 8.8 mΩ·cm^2, respectively, for a DG TR metal-oxide semiconductor field-effect transistor （MOSFET） by simulation. Compared with a conventional SOI LDMOS, a DG TR MOSFET with the same dimensional device parameters as those of the DG TR MOSFET reduces Ron,sp by 59% and increases BV by 6%. The extended trench gate synchronously acts as an isolation trench between the high-voltage device and low-voltage circuitry in a high-voltage integrated circuit, thereby saving the chip area and simplifying the fabrication processes.A low on-resistance （Ron,sp） integrable silicon-on-insulator （SOI） n-channel lateral double-diffused metal-oxide-semiconductor （LDMOS） is proposed and its mechanism is investigated by simulation. The LDMOS has two features： the integration of a planar gate and an extended trench gate （double gates （DGs））; and a buried P-layer in the N-drift region, which forms a triple reduced surface field （RESURF） （TR） structure. The triple RESURF not only modulates the electric field distribution, but also increases N-drift doping, resulting in a reduced specific on-resistance （Ron,sp） and an improved breakdown voltage （BV） in the off-state. The DGs form dual conduction channels and, moreover, the extended trench gate widens the vertical conduction area, both of which further reduce the Ron,sp. The BV and Ron,sp are 328 V and 8.8 mΩ·cm^2, respectively, for a DG TR metal-oxide semiconductor field-effect transistor （MOSFET） by simulation. Compared with a conventional SOI LDMOS, a DG TR MOSFET with the same dimensional device parameters as those of the DG TR MOSFET reduces Ron,sp by 59% and increases BV by 6%. The extended trench gate synchronously acts as an isolation trench between the high-voltage device and low-voltage circuitry in a high-voltage integrated circuit, thereby saving the chip area and simplifying the fabrication processes.

关 键 词：SOI electric field breakdown voltage trench gate specific on-resistance 

分 类 号：TN386.1[电子电信—物理电子学]