岛式FPGA芯片布局布线改进的实现  

Implementation of Placement and Routing Improvement for Island-Style FPGA Chips

作　　者：李明[1] 李艳[1] 陈亮[1] 于芳[1] 刘忠立[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《华南理工大学学报（自然科学版）》2012年第6期16-21,共6页Journal of South China University of Technology(Natural Science Edition)

基　　金："核高基"国家科技重大专项(Y1GZ212002)

摘　　要：针对FPGA布局过程与布线过程连接松散的问题,开发了一款改进的布局布线工具(IVPR).在布局过程中考虑了逻辑模块的引脚方向,以建立更准确的延迟预测,并预测逻辑模块在布线阶段使用的引脚方向,从而选择合适的延时值,使得布局与布线的结合更有效.针对高扇出线网,在布局过程中加入了线网终端对齐,并在布线阶段优先采用长线连接.以岛式FPGA芯片VS1000为例进行实验,结果表明,与经典的布局布线工具VPR相比,IVPR的电路延时降低了16.4%,布线资源利用率提高了1.9%.In order to overcome the loose coupling between FPGA（Field Programmable Gate Array） placement and routing,an improved placement and routing tool named IVPR is exploited.In IVPR,the directions of logic block pins are considered during the placement to perform a more precise delay forecast,and the possible directions of logic block pins during the routing are predicted to choose an appropriate delay.Thus,the combination between the placement and the routing becomes more effective.Moreover,for the high fanout in the netlist,the net terminal alignment is employed during the placement and the longline-priority strategy is adopted during the routing.Tested results on an island-style FPGA chip VS1000 show that,as compared with the typical placement and routing tool VPR,IVPR reduces the circuit delay by 16.4% and increases the routing resource utilization by 1.9%.

关 键 词：现场可编程门阵列 布局 布线 延时预测 线网终端对齐 

分 类 号：TN47[电子电信—微电子学与固体电子学]