基于逻辑结构的超前进位加法器的设计  

Design of Carry Look-ahead Adder Based on Logical Structure

作　　者：白首华[1] 胡天彤[1] 

机构地区：[1]郑州航空工业管理学院,河南郑州450015

出　　处：《山西电子技术》2012年第4期3-4,6,共3页Shanxi Electronic Technology

基　　金：院青年基金(厅级):超前进位加法器优化算法与设计的研究(No.2011103001)

摘　　要：通过对计算机加法器的研究,从门电路标准延迟模型出发,在对超前进位加法器逻辑公式研究的基础上,在主要考虑速度的前提下,给出了超前进位加法器的逻辑电路的设计方案。主要对16位、32位加法器的逻辑电路进行分析设计,通过计算加法器的延迟时间来对比超前进位加法器与传统串行进位链加法器,得出超前进位算法在实际电路中使加法器的运算速度达到最优。Through the research of computer adder, from the standard delay model of a gate and mainly considering the premise of speed, the paper gives the carry advance adder design scheme of the logic circuit. It mainly makes the analysis of the circuit design to the 16, 32-bit adder, through calculating the delay time to compare carry look-ahead adder with the traditional serial binary adder chain, and drawing a conclusion： the advanced carry algorithm makes adder operation speed to achieve the most optimal condition in the practical circuit.

关 键 词：串行进位链 超前进位加法器 时间延迟 

分 类 号：TP302.2[自动化与计算机技术—计算机系统结构]