基于UVM验证方法学的AES模块级验证  

AES Module Level Verification Based on UVM

作　　者：田劲[1] 王小力[1] 

机构地区：[1]西安交通大学微电子学系,陕西西安710049

出　　处：《微电子学与计算机》2012年第8期86-90,共5页Microelectronics & Computer

基　　金：国家自然科学基金项目(61172040)

摘　　要：分析了基于System Verilog语言的UVM(Universal Verification Methodology)高级验证方法学,并使用该方法学对AES(Advanced Encryption Standard)模块进行了功能验证.验证结果表明,此验证平台能够实时监测覆盖率,控制验证进程,优化验证事务.该方法提高了验证的效率验和证平台的可重用性,较好地满足了芯片验证需要.This paper analyzed an advanced verification methodology called UVM which based on system verilog language and verified the function of AES. As a result of verification, we can monitor coverage, control the platform and optimize the testbench and testcase. This Methodology can improve the verification efficiency and platform reuse. It well meets the needs of chip verification.

关 键 词：UVM验证方法学 SYSTEM VERILOG AES 随机约束 

分 类 号：TN4[电子电信—微电子学与固体电子学]