基于FPGA的多功能数字钟设计  

Design of multifunction digital clock based on FPGA

作　　者：纪欣然[1] 丁一[1] 梁致源[1] 

机构地区：[1]浙江大学控制科学与工程学系,浙江杭州310027

出　　处：《电子设计工程》2012年第16期177-179,共3页Electronic Design Engineering

摘　　要：文中简要介绍了一种基于FPGA的多功能数字钟设计方案。在实现数字钟计时、校时和整点报时等基本功能的基础上增加世界时钟功能,能够将北京时间快速转换为格林威治标准时。该方案采用VHDL和原理图相结合的设计输入方式,在QuartusⅡ开发环境下完成设计、编译和仿真,并在FPGA硬件开发板上进行测试,实验证明该设计方案切实可行,对FPGA的应用和数字钟的设计具有一定参考价值。This paper briefly introduces a design scheme of multifunction digital clock based on FPGA. On the basis of achieving basic functions such as timing, adjusting and chronopher, the scheme brings in new world-time function, which can convert Beijing Time to GMT quickly. The design input method of the scheme combines VHDL and block diagram. The digital clock is designed, compiled as well as simulated under Quartus II development environment, and tested on the FPGA hardware development board. The experiment verifies the design scheme, which offers references for the application of FPGA and the design of digital clock.

关 键 词：FPGA VHDL 数字钟 世界时钟 QuartusⅡ 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]