祖冲之序列密码算法IP核的设计与实现  

An IP Core Design and Implementation of ZUC Stream Cipher

作　　者：江丽娜[1] 高能[1] 马原[1] 刘宗斌[1] 

机构地区：[1]中国科学院信息工程研究所信息安全国家重点实验室,北京100195

出　　处：《信息网络安全》2012年第8期219-222,共4页Netinfo Security

基　　金：中国科学院战略性先导专项[XDA06010702];国家自然科学基金[70890084/G021102;61003274]

摘　　要：祖冲之序列密码算法是中国自主研究的流密码算法,是运用于下一代移动通信4G网络中的国际标准密码算法,该算法包括祖冲之算法(ZUC)、加密算法(128-EEA3)和完整性算法(128-EIA3)三个部分。目前,已有对ZUC算法的优化实现,而专门针对128-EEA3和128-EIA3的硬件实现与优化,尚未见公开发表的论文。文章设计了祖冲之序列密码算法的IP核,该IP核基于ZUC算法模块,同时支持128-EEA3和128-EIA3,并且保持ZUC模块的高吞吐率。最后,在Virtex-5 FPGA平台上对该IP核进行了实现,并对其性能进行了比较和分析。The ZUC stream cipher algorithm is a stream cipher algorithm designed by China with full intellectual property. It is one of the three international standard cryptology algorithms to be used in the forthcoming 4G mobile communication era and is composed of three parts： the ZUC algorithm （ZUC）, the encryption algorithm （128-EEA3） and the integrity algorithm （128-EIA3）, By now some works on the optimization towards ZUC have been published, yet hardware implementation and optimization towards 128-EEA3 and 128-EIA3 have not been seen in literature. This paper presents an IP core design for the ZUC stream cipher algorithm based on a ZUC module, maintaining the high throughput of the module, with support for both 128-EEA3 and 128-EIA3. We implemented this IP core on a Virtex-5 FPGA platform and then brought forward an evaluation of its performance.

关 键 词：祖冲之算法 128-EEA3算法 128-EIA3算法 FPGA IP核 

分 类 号：TN47[电子电信—微电子学与固体电子学] TN918.1