高速自应答异步双轨推通道设计  

Design of High-Speed Self-Acknowledgement Asynchronous Dual-Rail Push Channel

作　　者：杨延飞[1] 周端[2] 杨银堂[1] 彭瑶[1] 

机构地区：[1]西安电子科技大学微电子研究所,西安710071 [2]西安电子科技大学计算机学院,西安710071

出　　处：《计算机辅助设计与图形学学报》2012年第9期1211-1217,1225,共8页Journal of Computer-Aided Design & Computer Graphics

基　　金：国家自然科学基金(60725415;60971066);国家"八六三"高科技研究发展计划(2009AA01Z258;2009AA01Z260);"宽带隙半超导体"国家重点实验室基金(ZHD200904)

摘　　要：针对全局异步、局部同步片上网络中不同传输速率下的数据传输问题,提出一种高速异步双轨推通道.该通道中的单元采用自应答控制,在减小前向延时的同时提高了吞吐率;双轨数据的传输采用对称结构的2条独立传输链路,避免了复杂的时序设计,降低了传输链路间的干扰,保证了数据的可靠传输.最后基于0.18μm标准CMOS工艺,在不同温度、不同工艺角下对4级通道的性能进行测试.结果表明,采用文中的异步通道前向延时为70ps,吞吐量为4.46GHz,功耗为2.71mW,可满足高速、低功耗、高鲁棒性的片上通信需求.This paper proposes a novel high-speed asynchronous dual-rail push channel for the data transmission with varying transmission rate in globally asynchronous locally synchronous network-on- chip. With the self-acknowledgement control, the forward latency is reduced and the throughput is improved. Meanwhile, the asynchronous channel transmits dual-rail data through two independent transmission link with symmetric structure in order to avoid complex timing design, reduce transmission link interference and ensure reliable data transmission. Performance of four-stage channel has been verified under different fabrications and temperatures based on SMIC 0.18μm standard CMOS technology. Simulation results show that the forward latency is 70 ps, the average dynamic power dissipation is 2.71 mW with the throughput of 4.46 GHz, which can fulfill the requirements of high- speed, low power, highly robust on-chip communication.

关 键 词：异步通道 异步协议 高速低功耗 全局异步局部同步 片上通信 

分 类 号：TN402[电子电信—微电子学与固体电子学]