数字锁相环在位同步中的应用与实现  

Application and Implementation of Digital Phase Lock Loop in Symbol Timing Synchronization

作　　者：李庆坤[1] 全厚德[1] 李庆会 

机构地区：[1]军械工程学院,河北石家庄051000 [2]第二炮兵青州士官学校,山东青州262500

出　　处：《通信技术》2012年第9期29-32,35,共5页Communications Technology

摘　　要：给出了一种适用于数字接收机的位同步数字锁相环算法。首先分析了数字锁相环的各个组成部分,详细推导了数字锁相环路中环路滤波器参数、鉴相增益等各个参数的计算公式;然后利用Matlab分别仿真了环路对输入信号相位和频率阶跃的响应,对仿真结果进行了分析。仿真结果表明,采用数字锁相环的位同步电路对输入信号的相位和频率阶跃具有较好的跟踪性能。最后说明了在环路设计中应该注意的几个问题。A DPLL（Digital Phase Lock Loop） algorithm for the symbol timing synchronization of digital receiver is proposed.The component parts of the DPLL is analyzed first,the calculation formulas of various parameters including those of discriminator gain,and loop filter etc.are derived in detail;then with Matlab,the simulations on the responses of the step in phase and frequency of the input signals are done Matlab.The simulation results indicate that the symbol timing synchronization with DPLL can track the input signals in phase and frequency well.Some issues concerned in the design of loop are also described in the paper.

关 键 词：数字锁相环 鉴相增益 环路滤波器 数控振荡器 

分 类 号：TN919.3[电子电信—通信与信息系统]