数字中频相干解调数字锁相环设计和FPGA实现  

Implementation and design of DPLL for digital IF coherent demodulator

作　　者：洪龙龙[1] 陈星[1] 沈艳芳[1] 

机构地区：[1]北京航空航天大学电子信息工程学院,北京100191

出　　处：《电子测量技术》2012年第8期23-26,共4页Electronic Measurement Technology

摘　　要：数字中频相干解调器是基于软件无线电技术的数字中频接收机的首要部件,而其中的数字锁相环又是数字中频相干解调器的核心。数字锁相环是1个非线性系统,为了避开非线性分析的困难,本文利用数字锁相环与模拟锁相环在跟踪和捕获规律准等效的条件,阐述了一种实用有效的数字锁相环设计方法。该方法基于数字环z域模型与对应的模拟环s域模型的参数关联性,首先按设计要求,设计模拟环的模型参数,然后通过模拟环与数字环模型参数间的函数关系得到数字环的模型参数。仿真实验与FPGA实现表明,利用该方法设计实现的数字锁相环工作正常、稳定,主要技术指标与理论分析相符合。Digital IF coherent demodulator is the main components of the digital IF receiver, which is based on software radio technology. And DPLL is device core of demodulation. But DPLL is a nonlinear system, in order to avoid the difficulties of nonlinear analysis, the essay uses the equivalent conditions of DPLL and PLL in tracking and capture, presents a practical and effective method for the design of DPLL. This method is based on relevant parameters in z domain and corresponding s domain, according to the design requirements, designs parameters of PLL, and then through the relevant parameters to become DPLL parameters. Simulation based on FPGA show that, this method implements a DPLL which work normal, stable and the main technique index is compatible with the analysis theory.

关 键 词：数字锁相环 环路增益 锁入极限 拉入时间 相干解调 FPGA 

分 类 号：TN914[电子电信—通信与信息系统]