高速DAC与FPGA接口信号完整性的仿真分析  

Simulation analysis of signal integrity for interconnection between FPGA and DAC

作　　者：窦垭锡[1] 陈星[1] 高群福[1] 

机构地区：[1]北京航空航天大学电子信息工程学院,北京100191

出　　处：《电子测量技术》2012年第8期120-124,共5页Electronic Measurement Technology

摘　　要：在高速系统设计中,随着数字电路工作频率的提高,信号完整性问题变得无处不在,对电路稳定性影响很大。针对高速电路发展带来的信号完整性问题,借助Hyperlynx软件和IBIS模型对基于FPGA的400MHz高速DAC系统进行了信号完整性方面的仿真和分析,并且针对信号的反射和串扰问题进行了详细论述。研究结果表明,采取合适的方法可以有效的减小信号的反射和串扰,并且仿真的结果能给实际电路设计实现提供有价值的指导。In the high-speed digital system design, with the increase in frequency of digital circuits, signal integrity issues has a tremendous impact on the circuit stability. Aiming at the signal integrity problem created hy the development of modern high-speed circuit,the signal integrity of the system consisted by FPGA and DAC is simulated and analysed with HyperLynx and IBIS model,and in view of the signal reflection and crosstalk issues in detail. The results illustrate that the appropriate ways can effectively reduce the signal reflection and crosstalk, and the results can provide an experience in practice for projects.

关 键 词：高速信号仿真 信号完整性 HYPERLYNX IBIS模型 反射 串扰 

分 类 号：TN702[电子电信—电路与系统]