DLMS算法的脉动阵结构设计及FPGA实现  

Design of systolic array structure of DLMS algorithm and its FPGA implementation

作　　者：裴亮锋[1] 陈自力[1] 

机构地区：[1]军械工程学院,河北石家庄050003

出　　处：《现代电子技术》2012年第17期47-50,共4页Modern Electronics Technique

摘　　要：为了减小无人机数据链中的码间干扰,适应数据链对传输速度的要求,利用Verilog HDL设计DLMS算法,并在其中加入脉动阵结构,完成了均衡器的高速实现。仿真表明所设计的均衡器的最高频率可达298.063 MHz,这为以后设计更高频率或其他类型的高速均衡器指明了方向。In order to decrease the effect of inter-symbol interference in the UAV data link and meet the needs of the data transmission speed, the paper designs DLMS algorithm with systolic array structure using Verilog HDL, and achieves the high-speed equalizer, The simulation results show that the highest frequency of the designed equalizer reaches up to 298, 06SMHz, which points out the development direction for the design of the high-speed equalizer with higher frequencies or other types of equalizer,

关 键 词：脉动结构 DLMS 无人机 均衡器 FPGA 

分 类 号：TN715.34[电子电信—电路与系统]