一种应用于流水线ADC中的高性能采样保持电路  

A high-performance sample-and-hold circuit used in pipelined ADC

作　　者：罗斌 何庆领[2] 

机构地区：[1]安徽省科学技术馆,安徽省合肥市230088 [2]合肥工业大学计算机与信息学院,安徽省合肥市230009

出　　处：《中国科技信息》2012年第19期79-80,106,共3页China Science and Technology Information

摘　　要：基于SMIC 0.18um CMOS工艺设计了一种高速、高精度、高线性度的采样保持电路。采用全差分带增益自举电路的高增益、高带宽运放,以及改进的带衬底电压调整的栅压自举开关,有效增加输入信号带宽并减小采样保持电路的非线性。对设计的电路进行仿真,在输入信号幅值为2VP-P,频率为47.66MHz,采样频率为100MSPS时,采样保持电路建立时间为3.606ns,建立精度达0.004%,有效位数为17.2bit,无杂散动态范围达108.5dB。A high--speed, high-precision and high--linearity sample and-hold circuit is designed in SMIC 0. 18urn CMOS technology. It adopted a high-gain, high--bandwidth fully differential OP--Amp with gain bootstrap circuit, and an improved gate-- voltage bootstrap switch with substrate voltage adjustment, effectively increase the bandwidth of the input signal and decrease the nonlinearity of the sample--and--hold circuit. The simulation results show that when the amplitude of the input signal is 2VP--P, at the same time the frequency is 47.66MHz and the sampling frequency of 100MSPS, the setup time of the sample-and- hold circuit is 5.606ns, and the setup accuracy reaches 0.0004%. The ENOB of it is 17.2bit, and the spurious--free dynamic range reaches 108.47dB.

关 键 词：采样保持电路 流水线ADC 全差分运放 增益自举电路 栅压自举开关 

分 类 号：TN792[电子电信—电路与系统]