多相抽取滤波器的FPGA实现  

The Realization of Polyphase Decimation Filter on FPGA

作　　者：谢海霞[1] 孙志雄[1] 

机构地区：[1]琼州学院电子信息工程学院,海南三亚572022

出　　处：《电子器件》2012年第3期331-333,共3页Chinese Journal of Electron Devices

基　　金：海南省自然科学基金项目(611133);三亚市院地科技合作项目(2010YD33);三亚市院地科技合作项目(2011YD03)

摘　　要：信号的多相分解在多抽样率信号处理中有着重要的作用。介绍了多相分解的基本理论,结合FIR抽取滤波器的多相分解形式,用Verilog HDL语言来实现2倍抽取滤波器的多相结构,QuartusⅡ软件仿真输出波形,并且用MATLAB对仿真结果进行验证并作比较。结果正确,最后将编程数据文件下载到FPGA芯片上。多相抽取滤波器的设计方法是可行的,整个设计过程由软件实现,参数易于修改。Polyphase decomposition played an important role in multi-rate signals processing.The paper introduced the polyphase decomposition theory,combined with the polyphase decomposition form of the FIR decimation filter,realized 2 times polyphase structure decimation filter with Verilog HDL,simulated waveform by Quartus,verified the result and compared it with the theory value by MATLAB,which was correct.Finally,the programmable file was downloaded to FPGA.The design method of polyphase decimation filter was feasible;the entire design process was realized by software,easy to modify the parameter.

关 键 词：抽取滤波器 多相分解 FPGA VERILOG HDL 

分 类 号：TN911.72[电子电信—通信与信息系统]