视频处理器中电荷泵锁相环设计  

Design of Charge Pump PLL in the Video Processor

作　　者：邓文娟[1] 邹继军[1] 刘树博[1] 王嵩[1] 陈坚[1] 陈培根[1] 

机构地区：[1]东华理工大学机械与电子工程学院,江西抚州344000

出　　处：《半导体技术》2012年第10期750-754,共5页Semiconductor Technology

基　　金：国家自然科学基金资助项目(61067001)

摘　　要：为产生一个与视频信号中的行同步信号严格同步的时钟信号,设计了一种数模混合结构的电荷泵锁相环(PLL)电路。通过对锁相环电路中鉴频鉴相器、电荷泵电路、振荡器电路设计适当改进,实现了性能稳定的时钟信号。采用中芯国际公司的0.35μm 2P4M双层多晶硅四层金属3.3 V标准CMOS工艺,使用Simulink软件进行了系统级仿真、Spectre软件进行了电路级仿真、Hsim软件进行了混合仿真。结果表明,环路输出频率27 MHz时钟信号,占空比达到50.141%,输入最大2 Gbit/s像素信号条件下,时钟抖动小于350 ps,锁定时间小于30μs,芯片的工作达到设计要求。In order to generate a pulse which is strictly synchronized with the line synchronization signal of the video decoder,a mixed analog-digital structure of the charge pump phase-locked loop（PLL）was designed.By appropriate improving the circuit design of the phase frequency detector,charge pump and voltage-controlled oscillator in PLL,a stable performance of the clock signal was achieved.The PLL fabricated by SMIC 0.35 μm2P4M（double-polysilicon,four metal）3.3 V standard complementary metal-oxide-semiconductor（CMOS）process,which used Simulink soft to system level simulation,used Spectre soft to circuit level simulation,used Hsim soft to mix simulation.Test results show that loop the output of 27 MHz clock signal,the duty cycle of 50.141%,and the jitter of output system clock is less than 350 ps on the condition of input maxim 2 Gbit/s pixel data signal,the lock time is less than 30 μs,which meets the design requirement.

关 键 词：视频解码芯片 同步信号 电荷泵锁相环 互补型金属氧化物半导体 时钟抖动 

分 类 号：TN432[电子电信—微电子学与固体电子学]