MOS电流模逻辑分频器设计  

The Design of MOS Current Mode Logic Frequency Divider

作　　者：梁蓓[1,2] 马奎[2] 傅兴华[2] 

机构地区：[1]贵州大学科技学院,贵州贵阳550025 [2]贵州大学微纳电子技术重点实验室,贵州贵阳550025

出　　处：《微电子学与计算机》2012年第10期157-160,165,共5页Microelectronics & Computer

基　　金：贵州省重点实验室建设项目计划([2010]4006)

摘　　要：用参数已经优化的MCML(MOS电流模逻辑)电路设计了锁存器,对锁存器的功耗及延迟进行了仿真分析;基于该锁存器分别设计了一个二分频和四分频电路,二分频电路的最高工作频率达到7.7GHz.四分频电路采用两个二分频电路直接级联,由于无缓冲连接,不仅减小了第一级的输出节点电容,同时减小了芯片的面积.电路仿真均在SMIC 0.13μmCMOS工艺下完成.The MCML （MOS current mode logic） latch is designed with optimized parameters. Its power consumptionand delay is analyzed and simulated. Based on this latches, the 1 ： 2 and the 1：4 frequency divider is designed, respectively. The maximum operating frequency of the 1：2 frequency divider is 7.7 GHz. The 1：4 frequency divider has be realized by two 1 ： 2 frequency dividers in cascade. Without buffers, the 1.. 4 frequency divider reduce the first stage output node capa-citance, and reduce the area of the chips. Circuits were simulated in the SMIC 0.13t^m CMOS technology.

关 键 词：MCML 锁存器 分频器 源耦合逻辑 

分 类 号：TN403[电子电信—微电子学与固体电子学]