符合CCSDS标准的动态可重构LDPC编码器的FPGA设计  

Design of Dynamically Reconfigurable LDPC Encoder Based on FPGA According to CCSDS Criteria

作　　者：邱鹏文[1] 柏鹏[2] 李明阳[2] 

机构地区：[1]空军工程大学理学院,陕西西安710051 [2]空军工程大学综合电子信息系统与电子对抗技术研究中心,陕西西安710051

出　　处：《电视技术》2012年第21期59-62,70,共5页Video Engineering

摘　　要：CCSDS标准的LDPC生成矩阵具有分块循环特征,并且各种码率的生成矩阵的校验部分都可以分解为8×x的形式,提出利用CCSDS标准的LDPC的特点设计动态可重构LDPC编码器。首先提出了LDPC编码器码速率重构的4种模型,然后分析了功能重构的关键技术模块,最后对码速率重构进行了仿真,并对仿真结果和综合结果进行了分析,结果与理论分析一致。CCSDS criteria LDPC generator matrix has the characteristic of block circulation, checking part of each code speed generator matrix can be disassembled into the form of 8 x. According to the characteristic of CCSDS criteria LDPC, Dynamically Reconfigurable LDPC encoder is proposed. Firstly, four models of code speed reconfiguration of LDPC encoder a proposed. Then key technology of function reconfiguration is analyzed. Finally, code speed reconfiguration is simulated, the results of simulation and integration are analyzed which are consistent to theoretical analysis.

关 键 词：分块循环 可重构LDPC编码器 码速率重构 功能重构 

分 类 号：TN919.8[电子电信—通信与信息系统]