基于Avalon总线的非标准以太网控制器IP核设计  

The IP Core Design of Non-standard Ethernet Controller Based on Avalon Bus

作　　者：薛毅[1] 彭建朝[1] 许向众[1] 

机构地区：[1]北京工业大学,100124

出　　处：《微计算机信息》2012年第10期176-178,共3页Control & Automation

摘　　要：本文根据以太网控制器结构特点,提出了一种非标准以太网控制器的IP软核设计方案。基于Avalon总线交换架构,该IP核能快速方便地搭建在SOPC系统之中,支持了嵌入式系统中的网络通信应用。该以太网IP核采用Verilog HDL硬件描述语言设计,遵循软件工程自顶向下的设计方法,体现了在多时钟域操控协同工作的技术特点。最后给出了该IP模块所进行功能的测试与验证。Based on Ethernet Controller structural features, a non-standard Ethernet controller IP core design is mentioned on this pa- per. Avalon bus-based switching architecture, the IP is quickly and easily built into the SOPC system to support network communi- cation applications in embedded systems. The Ethernet IP core using Verilog HDL hardware description language design follows the software engineering, top-down design approach, which reflecting the technical characteristics of collaborative work in the manipula- tion of multi-clock domain. Finally, the IP module for functional testing and verification is succeeded.

关 键 词：关键字 以太网控制器 IP核设计 AVALON总线 

分 类 号：TP368[自动化与计算机技术—计算机系统结构]