基于FPGA的串行定时器设计  

Design of serial controlled timers based on FPGA

作　　者：李克俭[1] 付杰[1] 蔡启仲[1] 吴笔迅[1] 

机构地区：[1]广西工学院电气与信息工程学院,广西柳州545006

出　　处：《广西工学院学报》2012年第3期61-65,共5页Journal of Guangxi University of Technology

基　　金：广西科学基金项目(桂科自2011GXNSFA018153)资助

摘　　要：为实现因控制芯片内部定时器数量有限而难以满足不断提高的控制需求,在外扩定时器方面,介绍了一种基于FPGA的串行控制的定时器设计,并通过使用FPGA内部的RAM结合顺序控制方式,可以在极短的周期内快速访问每一个定时单元,完成相应的定时工作;当定时完成后,通过中断方式通知外部芯片定时结束,并自动载入上次定时初始值,实现了外部控制芯片可以在任何时刻访问各个定时单元,获取定时状态与定时中间值.实验结果表明系统运行正常,满足要求.As the internal timers on control chip are small, the external timers are required to meet the needs of controlling. The design of serial controlled timers based on FPGA is presented. By using the sequential control based on the internal RAM on FPGA, every timing unit can be accessed during a tiny period, and the work of access can be accomplished accordingly. The interrupt mode can be used in notifying external chip of the end of timing and then original value of last time can be loaded automatically when the process of timing is finished. Exterior control chip can access every timing unit anytime, acquiring timing state and intermediate value. The test results indicate that the system works well and can meet the needs of controlling.

关 键 词：FPGA IP VERILOG 定时器 

分 类 号：TP23[自动化与计算机技术—检测技术与自动化装置]