基于TSC695F和FPGA的CAN总线接口设计  

Design of CAN Bus Interface Based on TSC695F and FPGA

作　　者：武星星[1] 刘金国[1] 周怀得[1] 孔德柱[1] 

机构地区：[1]中国科学院长春光学精密机械与物理研究所,长春130033

出　　处：《计算机测量与控制》2012年第11期3032-3034,3076,共4页Computer Measurement &Control

基　　金：国家自然科学基金(61108066)

摘　　要：新一代空间相机控制器采用具有高可靠性的32位处理器TSC695F和Flash型FPGA APA600作为核心控制单元,采用CAN总线与小卫星平台上各单元通信;由于TSC695F采用独立的32位数据线和地址线,而CAN总线控制器SJA1000采用8位分时复用的数据线和地址线;且TSC695F和SJA1000的地址线和数据线采用5V电平,APA600的输入输出接口采用3.3V电平,需要根据读写过程中数据流向对电平转换芯片的方向进行控制;提出了一种基于APA600的TSC695F与SJA1000的接口逻辑电路设计方法,给出了VHDL源码和在TSC695F中使用该CAN总线接口的具体方法;在实验中使用逻辑分析仪对实际工作过程中时序参数进行测量,实验结果表明采用本文的设计满足CAN总线接口时序要求,可以实现空间相机控制器与星上其他单元可靠的通讯。High reliable 32 bit processor TSC695F and FLASH type FPGA APA600 are used as core units in new generation of space camera controller. Units on small satellite platform use CAN bus as communication data bus. Separate 32 bit data bus and address bus are used in TSC695F while CAN controller SJA1000 adopts tlme--sharing multiplexing data and address bus. In addition data and address bus of TSC695F and SJA1000 use 5V electrical level. Input and output interfaces of APA600 use 3.3V electrical level. So direction of electrical level transformer should be controlled according to data flow direction in read and write process. A design method of interface logic circuit of TSC695F and SJA1000 based on APA600 was put forward. VHDL codes and specific method to use this CAN bus interface were presented. In experiments logic analyzer was used to measure the time parameters in process of practical work. Results o^f experiments indicated that de- sign of this paper satisfied time sequence demand of CAN bus interface and reliable communication between space camera controller and other units on the satellite could he realized.

关 键 词：FPGA TSC695 CAN总线 

分 类 号：TP336[自动化与计算机技术—计算机系统结构]