一种高分辨率深度图实时提取算法与硬件实现  

Real-time Extraction Algorithm of High Resolution Depth Map and Hardware Implementation

作　　者：王建伟[1] 滕国伟[1,2] 李贺建[1] 邹雪妹[1] 

机构地区：[1]上海大学通信与信息工程学院,上海200072 [2]上海国茂数字技术有限公司,上海201204

出　　处：《电视技术》2012年第23期21-24,46,共5页Video Engineering

基　　金：上海市科委科技项目(10510500500)

摘　　要：深度提取问题往往由于其巨大的立体匹配计算量成为整个立体视觉系统实现效率的瓶颈,对于高分辨率的视差图尤甚。针对深度图提取不能满足3D系统实时应用的现状,提出了一种基于硬件的深度图实时提取算法;改进了传统的CT变换,提出了大范围稀疏CT变换进行立体匹配,利用RAM资源以Verilog程序在FPGA中加以实现;得出视差图像每一个像素对应的视差,速度是PC软件实现的200倍以上,可实时应用,且支持分辨率高达1 920×1 080的视差图。Depth map extraction is always the efficiency bottleneck of the stereo vision system because of the tremendous computing of stereo matching. For the case that the depth map estimation can not meet the 3D real-time system application, a real-time depth map estimation algorithm based on hard- ware is proposed in this paper. The traditional census transform is modified and a vast sparse census transform algorithm is presented for stereo match, with the verilog programme implemented in FPGA upon RAM resources. The disparity of every pixel can be extracted in real time which is more than 200 times faster than when compared to a software program operating on a conventional computer. The scheme is appropriate for the disparity maps resolution up to 1 920 × 1 080.

关 键 词：FPGA 深度 视差 实时 主体电视 

分 类 号：TN919.82[电子电信—通信与信息系统]