智能模数控制型全数字锁相环的研究  

The research on all digital phase-locked loop of intelligent module control type

作　　者：陈高峰[1] 庞辉[1] 洪琪[1] 何敏[1] 

机构地区：[1]安徽大学电子信息工程学院,安徽合肥230601

出　　处：《安徽大学学报（自然科学版）》2012年第6期51-56,共6页Journal of Anhui University(Natural Science Edition)

基　　金：863计划资助项目(2009AA012201);专用集成电路与系统国家重点实验室开放基金资助项目(10KF014);安徽大学全日制研究生学术创新研究强化基金资助项目

摘　　要：由K模可逆计数器构成的传统数字锁相环可简单实现,但存在缩短捕获时间与减小同步误差之间的矛盾,而且获得的频带宽度较窄,因此设计了一种智能模数控制型全数字锁相环.其能够根据环路工作的不同阶段自动调整K值的大小,进而缩短捕获时间和减小同步误差.采用一个特殊的鉴频锁存器控制分频器的系数,能够调整环路的中心频率和扩宽频带宽度.The realization of the traditional digital and phase-locked loop which consists of K reversible counter is simple, but there is a contradiction between shortening the time of capture and the synchronization error, and the bandwidth of the loop is narrower. Therefore, authors designed the digital phase-locked loop of intelligent module control, which could work according to the different stages of loop automatically and adjust the size of the K value. It could shorten the time of the capture and reduce the synchronization error. Since the coefficient of frequency divider was controlled by a special frequency discriminator latched, the center frequency loop was adjusted and the frequency bandwidth was broadened.

关 键 词：全数字锁相环 智能模数控制器 鉴频锁存器 VERILOG HDL 

分 类 号：TN47[电子电信—微电子学与固体电子学]