DC-DC电源管理芯片中死区时间的研究  

Study on Dead Time of DC-DC Power Management IC

作　　者：郝志燕[1] 姜岩峰[1] 鲍嘉明[1] 鞠家欣[1] 

机构地区：[1]北方工业大学信息工程学院微电子系,北京100144

出　　处：《微电子学》2012年第6期770-773,共4页Microelectronics

基　　金：教育部新世纪优秀人才计划(2008)资助项目

摘　　要：分析了带同步整流开关的降压型DC-DC电源管理芯片,介绍了衬底噪声中闩锁效应的产生机理,提出加入死区时间控制同步整流开关信号的方法来避免闩锁效应,但是,死区时间设置不合理会产生功率损耗。以频率为1MHz、输出电压为2.5V、最大输出电流为2A的降压型DC-DC电源管理芯片为例,对其进行仿真。结果表明,死区时间的长短会影响功率管的开关损耗,负载的大小也会影响合适的死区时间。A buck DC-DC power management IC with synchronous rectification was analyzed, and generation mechanism of latch-up in substrate noise was described. A method to avoid latch up by introducing dead time to control synchronous rectifier switch signal was proposed. However, improper dead time would generate power loss. With a 1 MHz 2. 5 V/2 A buck IX-IX; power management IC as an example, effects of dead time on the circuit was simulated. Simulation results showed that the length of dead time could affect the switching losses of power MOSFET, and the load size could also affect proper dead time.

关 键 词：闩锁效应 死区时间 电源管理 

分 类 号：TN431.1[电子电信—微电子学与固体电子学]