高性能并行Turbo译码器的VLSI设计  

VLSI Design of High Performance Parallel Turbo Decoder

作　　者：陈绪斌[1] 曹嘉麟[1] 陈赟[1] 曾晓洋[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《计算机工程》2012年第23期255-258,共4页Computer Engineering

基　　金：国家"863"计划基金资助项目(SQ2008AA01ZX1480432);国家科技重大专项基金资助项目"新一代宽带无线移动通讯网"(2011ZX03003 003 03)

摘　　要：提出一种高度并行的Turbo译码器。该译码器包含32个并行的基4子译码器,采用改进的滑窗译码流程和存储单元划分方案,使吞吐率最高提升43.2%。在SMIC 0.13 m工艺下,该译码器包含194万等效门,在294 MHz时钟频率和5.5次迭代下,吞吐率可达1.19 Gb/s,满足4G移动通信标准LTE Advanced的峰值吞吐率要求。This paper presents a highly parallel Turbo decoder architecture.It utilizes 32 parallel radix 4 component decoders and its throughput is increased by 43.2% at most with modified sliding window and memory partition scheme.The proposed decoder is implemented in SMIC 0.13 m technology,which has 1.94 M equivalent gate counts and achieves 1.19 Gb/s running at 294 MHz with 5.5 iterations.It meets the peak data rate requirement of 4G mobile communication standard LTE Advanced.

关 键 词：TURBO码 译码器 并行结构 基4 4G移动通信 

分 类 号：TP331[自动化与计算机技术—计算机系统结构]