MPMC高速存储器接口IP核设计  

A Design of High-speed Memory Interface IP Core Based on MPMC

作　　者：曹一江[1] 马宁[1] 王建民[1] 

机构地区：[1]哈尔滨理工大学应用科学学院,黑龙江哈尔滨150080

出　　处：《哈尔滨理工大学学报》2012年第6期75-80,共6页Journal of Harbin University of Science and Technology

基　　金：黑龙江省教育厅科学技术研究项目(12511079)

摘　　要：为实现用户逻辑与片外存储器间的高速通信,设计一种基于MPMC的高速总线接口IP核.通过对读写数据缓存、地址判断以及NPI传输模式的动态选择,进而实现任意地址、任意长度的突发数据传输,并支持传输等待,最终扩展了MPMC IP核的功能,提高了对片外存储器的访问速率.实验表明,所设计的接口IP核数据吞吐率最高可达742.6 MB/s.In this paper,we design a high-speed interface IP core based on MPMC,which implements high-speed data transmission between user logic and memory.By caching reading and writing data,judging addresses,and selecting transfer modes in dynamic,the IP core can realize burst data transmission of any address or length,and it also does supports transmission waiting mode.In this way,our design extends the functionality MPMC IP Core.The verification shows that the IP Core has a throughput that up to 742.6MByte/s.

关 键 词：存储器控制器 通信接口 用户IP核 

分 类 号：TP237[自动化与计算机技术—检测技术与自动化装置]