A novel latch-up free SCR-LDMOS with high holding voltage for a power-rail ESD clamp  

作　　者：潘红伟 刘斯扬 孙伟锋 

机构地区：[1]National ASIC System Engineering Research Center,Southeast University

出　　处：《Journal of Semiconductors》2013年第1期53-57,共5页半导体学报（英文版）

基　　金：Project supported by the Natural Science Foundation of Jiangsu Province (No.BK2011059);the Program for New Century Excellent Talent in University (No.NCET-10-0331)

摘　　要：The low snapback holding voltage of the SCR-LDMOS device makes it susceptible to latch-up failure,when used in power-rail ESD（electro-static discharge） clamp circuits.In order to eliminate latch-up risk,this work presents a novel SCR-LDMOS structure with an N-type implantation layer to achieve a 17 V holding voltage and a 5.2 A second breakdown current.The device has been validated using TLP measurement analysis and is applied to a power-rail ESD clamp in half-bridge driver ICs.The low snapback holding voltage of the SCR-LDMOS device makes it susceptible to latch-up failure,when used in power-rail ESD（electro-static discharge） clamp circuits.In order to eliminate latch-up risk,this work presents a novel SCR-LDMOS structure with an N-type implantation layer to achieve a 17 V holding voltage and a 5.2 A second breakdown current.The device has been validated using TLP measurement analysis and is applied to a power-rail ESD clamp in half-bridge driver ICs.

关 键 词：ESD protection ESD robustness SCR-LDMOS LATCH-UP holding voltage 

分 类 号：TN386.1[电子电信—物理电子学]