多核处理器验证中存储数据错误快速定位机制  

A fast location mechanism on memory data error for multi-core processors verification

作　　者：周宏伟[1] 邓让钰[1] 李永进[1] 晏小波[1] 窦强[1] 

机构地区：[1]国防科技大学计算机学院,湖南长沙410073

出　　处：《国防科技大学学报》2012年第6期1-6,共6页Journal of National University of Defense Technology

基　　金：国家"核高基"重大专项资助项目(2009ZX01028-002-002);国家自然科学基金资助项目(61103011;61170045)

摘　　要：提出并实现的一种数据错误快速定位机制(Fast Fault Location Mechanism,FFLM)面向多核处理器存储系统的功能验证,FFLM基于硬件仿真器构建多端口存储器黄金模型,通过在仿真过程中实时监控存储系统与处理器核之间的访存报文,在线比较被测系统访问真实存储器的数据与黄金模型中的对应数据是否一致,在错误数据从存储系统送入处理器核的时刻就能够发现数据错误。与传统方法相比,FFLM具有仿真速度快、硬件资源代价低以及定位错误时间短的优点。对自主设计的CMP-16多核处理器进行仿真时的统计数据表明:使用FFLM后定位数据错误的速度能够比未使用FFLM时平均提高6.5倍。A fast fault location mechanism on memory data error, which is called FFLM for a self-made CMP-16 multi-core processor＇ s functional validation, is proposed and realized. FFLM builds a multi-port golden memory model based on the hardware emulation accelerator. It monitors the packages of memory access between memory system and processor cores during the emulation, real-time compares the data from real memory system being tested and the data from golden memory model, judges whether they are consistent, and finds the errors once any wrong data is sent to processor core from memory system. Compared with traditional ways, FFLM has the advantages of fast emulation speed, low hardware cost and low fault Location time cost. Statistical results from the emulation for a self-made CMP-16 multi-processor show that FFLM improves the speed of date fault location in memory system by 6.5 times averagely.

关 键 词：多核处理器 验证 存储数据错误 定位机制 

分 类 号：TP302.1[自动化与计算机技术—计算机系统结构]