一种基于层次位线缓冲的异步片上路由器  

A novel asynchronous on-chip router based on hierarchical bit-line buffer

作　　者：石伟[1] 郭御风[1] 王蕾[1] 龚锐[1] 窦强[1] 

机构地区：[1]国防科技大学计算机学院,湖南长沙410073

出　　处：《国防科技大学学报》2012年第6期7-13,共7页Journal of National University of Defense Technology

基　　金：国家"核高基"重大专项资助项目(2009ZX01028-002-002);国家自然科学基金资助项目(61202481;61202123;61202122)

摘　　要：片上缓存资源是片上路由器的重要组成部分,其结构好坏直接关系到片上互联网络的实现复杂度、整体性能及功耗开销。鉴于异步电路的握手工作方式,异步路由器一般采用基于移位寄存器的异步FIFO(First In First Out)实现片上缓冲,这种结构导致了报文传输延迟及数据翻转次数增加。提出一种基于层次位线缓冲的异步FIFO结构,设计实现了一种新的异步路由器结构。相对于传统异步路由器,新的异步路由器能够有效降低路由器设计的硬件复杂度,减少数据的冗余翻转,降低功耗。实验结果表明在相同配置的情况下,新异步路由器面积降低了39.3%;当异步FIFO深度为8的时候,新异步路由器能够获得41.1%的功耗降低。Buffer resources are key components of the on-chip router, and their structures exert significant influence on the performance and power consumption of the interconneetion network. In general, asynchronous FIFO based on shift registers is adopted to implement on-chip buffer resources. Packets transmitted traverse the FIFO queue step by step, leading to higher propagation delay of packets and larger transition counts in the circuit. In this research, an asynchronous FIFO based on hierarchical bit-line buffer is proposed, and then a new asynchronous on-chip router is presented in detail. Compared with the traditional asynchronous router, the newly presented one has lower hardware complexity and power consumption. Experiments show that the new router can achieve 39.3 % area saving and 41.1% power reduction when the depth of asynchronous FIFO is configured with 8.

关 键 词：异步电路 片上网络 低功耗 层次位线缓冲 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]