FPGA的静态功耗分析与降低技术  

Static Power Analysis and Decrease Technology of FPGA

作　　者：曹正州[1] 曹靓[1] 

机构地区：[1]中国电子科技集团公司第58研究所,江苏无锡214035

出　　处：《电子与封装》2013年第1期26-29,共4页Electronics & Packaging

摘　　要：FPGA已经被广泛用于实现大规模的数字电路和系统,随着CMOS工艺发展到深亚微米,芯片的静态功耗已成为关键挑战之一。文章首先对FPGA的结构和静态功耗在FPGA中的分布进行了介绍。接下来提出了晶体管的漏电流模型,并且重点对FPGA中漏电流单元亚阈值漏电流和栅漏电流进行了详细的分析。最后根据FPGA的特点采用双阈值电压晶体管,关键路径上的晶体管采用低阈值电压栅的晶体管,非关键路径上的晶体管采用高阈值电压栅的晶体管,以此来降低芯片的静态功耗。FPGA has become quite popular for implementing digital circuits and systems, but when CMOS technology scaled down to deep sub micrometer range, the static power of chip has becoming one of the key challenges. This paper first introduces the architecture of FPGA and the distributing of static power in FPGA. Then brings forward the leakage model of transistor, and primary analyses the subthreshold and gate leakage in FPGA. At last Dual- Vt transistors based architecture of FPGA are used to decrease the static power through using low Vt transistors in critical path and using high Vt transistors in non-critical path.

关 键 词：FPGA 亚阈值漏电流 布线开关 双阈值电压 

分 类 号：TN402[电子电信—微电子学与固体电子学]