面向微处理器时钟发布的硅基无线发射器设计  

Design and Realization of Wireless Clock Distribution Transmitter Based on Folded Antennas Integrated on Silicon Substrate

作　　者：李晋文[1] 何小威[1] 张民选[1] 

机构地区：[1]国防科学技术大学计算机学院,长沙410073

出　　处：《上海交通大学学报》2013年第1期23-27,共5页Journal of Shanghai Jiaotong University

基　　金：国家高技术研究发展计划(863)项目(2012AA01A301);国家自然科学基金项目(60873212)资助

摘　　要：基于硅基天线和电磁波传输的无线互连技术,设计实现了一种面向微处理器的无线时钟分布发射器电路,包括一个长2.6mm、宽30μm、集成在硅衬底(电阻率为10Ω.cm)上的偶极折叠天线、高频锁相环、驱动和匹配电路.其中,硅基折叠天线提高了芯片的面积利用率,并通过在硅衬底与散热金属之间引入金刚石介质来提高折叠天线的传输增益.同时,为了减小信号传输功率的损失,在电路与硅基天线之间进行了阻抗共轭匹配,设计实现了中心工作频率11GHz的低噪声锁相环,在频率偏移为3、10MHz处的相位噪声分别达-116、-127dBc/Hz.结果表明,所设计的发射器有效面积为0.85mm2,能够提供低抖动、稳定的高频全局时钟源.Based on wireless interconnect technique using antennas integrated on silicon substrate and elec- tromagnetic waves, a transmitter of wireless clock distribution for microprocessors was designed and real- ized. It consists of a 2.6 mm long, 30 μm wide folded dipole antenna integrated on 10 Ω. cm silicon sub- strate, a high frequency phase locking loop （PLL）, driving and matching circuits. The on-chip folded an- tenna utilizes chip area effectively, and its transmission gain is improved by employing diamond between silicon substrate and heat sink. The central frequency of the proposed PLL is 11 GHz, and simulated phase noise achieves --116 and --127 dBc/Hz at 3 and 10 MHz offset, respectively. Impedance matching be- tween antenna and circuit is performed in order to reduce transmission power loss. The simulated results indicate that this transmitter occupies 0.85 mm2 effective area, which can provide low jitter, stable high frequency global clock.

关 键 词：折叠天线 无线互连 锁相环 传输增益 

分 类 号：TN386.1[电子电信—物理电子学]