新型总线中并行CRC算法的设计与实现  

Parallel CRC algorithm design and implementation of new bus

作　　者：杜瑞[1] 张伟功[1] 邓哲[1] 朱晓燕[1] 

机构地区：[1]首都师范大学北京市高可靠嵌入式系统技术工程研究中心,北京100048

出　　处：《计算机工程与设计》2013年第1期131-135,共5页Computer Engineering and Design

基　　金：国家自然科学基金项目(61170009)

摘　　要：为了对动态可重构高速串行总线UM-BUS进行差错控制,提出了一种用于新型总线数据校验的四通道并行CRC算法。根据UM-BUS的多通道并发通信方式和通道动态组织特点,采用四体FIFO进行数据缓冲存储,并设计了满足总线特点的四通道并行CRC编解码器。在此基础上,给出了它的FPGA实现方案和仿真结果。该并行CRC编解码器,可实时计算总线通信数据的CRC校验码,已成功的应用于动态可重构高速串行总线系统中,实现对突发错误的实时检测,通信速率达到100Mbps/通道。To control errors of dynamically reconfigurable high-speed serial bus UM-BUS, a four-channel parallel CRC algorithm for new bus is presented. Based on UM-BUS multi-channel data concurrent transmission and channel dynamic organization cha- racteristic, four-body FIFO is used for data buffering. And four-channel parallel CRC codec that meet the characteristics of new bus are designed. On this basis, its FPGA implementation and simulation results are given. The parallel CRC codec can real-time compute CRC of UM-BUS and is successfully applied to dynamically reconfigurable high-speed serial bus system, realize the burst error detection and communication rate reached 100Mbps/channel.

关 键 词：循环冗余校验码(CRC) 高可靠嵌入式系统 故障容错 动态重构 高速串行总线 

分 类 号：TN911[电子电信—通信与信息系统]