采用神经MOS晶体管的低压四象限模拟乘法器的设计  

Design of Low Voltage Four quadrant Analogue Multiplier Using Neuron MOS Transistor

作　　者：管慧[1] 汤玉生[1] 

机构地区：[1]上海交通大学微电子技术研究所,200030

出　　处：《固体电子学研究与进展》2000年第2期144-151,共8页Research & Progress of SSE

摘　　要：神经 MOS晶体管是最近几年才发明出来的一种高功能度的器件。本文以新开发的神经MOS晶体管的 SPICE宏模型为模拟和验证的工具 ,讨论了采用这种器件实现低压四象限模拟乘法器的系统化设计思想和方法。基于这种设计思想和方法 ,设计了一种大输入范围的低压(± 1 .5V)四象限模拟乘法器电路 ,给出的模拟结果验证了理论分析。The neuron MOS transistor is a recently invented device with high functionality. In this paper, a systematic approach for designing four quadrant analogue multiplier with low supply voltage requirements realized by using neuron MOS transistors is discussed. This approach is based on a new macromodel of neuron MOS transistor proposed by authors, which is used as a means of design and verification. A low supply (±1.5 V) four quadrant analogue multiplier with large input dynamic range is proposed on the basis of the approach, and the simulation results are given to verify the theoretical analyses.

关 键 词：半导体晶体管 模拟乘法器 神经MOS 四象限 

分 类 号：TN322[电子电信—物理电子学] TN432