一种低功耗图像压缩芯片的设计与实现  

Design and Implementation of a Low-Power JPEG Compressor IC

作　　者：刘守浩[1] 谷荧柯[1] 谢翔[1] 李国林[2] 童凯[2] 李晓萌[1] 

机构地区：[1]清华大学微电子学研究所,北京100084 [2]清华大学电子工程系,北京100084

出　　处：《微电子学》2013年第1期47-50,55,共5页Microelectronics

摘　　要：设计实现了一款低功耗小面积的JPEG图像压缩芯片。该压缩芯片采用4×4分块方式,每个4×4块的一维DCT运算只需要1次乘法。二维DCT中间转置结构采用一种新颖的实现方式,与传统的实现方式相比,减少了37.5%的延时和51%的面积。设计的电路采用UMC18工艺流片实现,芯片的面积和功耗分别为0.46mm2和0.9mW。测试结果显示,该图像压缩芯片可以在实现较高压缩比(大于80%)的同时获得较好的图像质量(PSNR大于30dB)。A low-power and small-area JPEG compressor IC was designed and implemented,in which 4×4 divided-blocks were used to reduce hardware complexity.The 4×4 compressor employed an optimized 1D-DCT algorithm,which contained only one multiplication.A new controlling architecture with 16 registers was used in transition buffer of 2D-DCT,which reduced 37.5% of latency and 51% of area,compared with traditional transposition architecture（two-RAM architecture）.Implemented in 0.18 μm CMOS process,the JPEG compressor chip had an area of 0.46 mm2 and a power consumption of 0.9 mW.Test results showed that the JPEG compressor IC achieved both high compression ratio（over 80%） and high quality image reconstruction（PSNR over 30 dB）.

关 键 词：JPEG 图像压缩 低功耗 芯片设计 

分 类 号：TN492[电子电信—微电子学与固体电子学]