高速数据采集卡DDR控制器的设计与实现  

Design and Implementation of DDR Controller in High-speed Data Acquisition Card

作　　者：王晓娇[1] 张治中[1] 

机构地区：[1]重庆邮电大学 通信网与测试技术重点实验室,重庆400065

出　　处：《电视技术》2013年第5期64-67,共4页Video Engineering

基　　金：国家科技重大专项(2012ZX03001021-004);重庆市成果转化项目(KJzh10204);科技部中小型企业技术创新基金项目(09C26215115488)

摘　　要：针对现有DDR控制器对DDR存储器中数据进行读写管理的不足,设计了一种基于FPGA实现的高速数据采集卡DDR控制器,提出了一种基于多个净荷包组装和转义思想的数据处理方法,以及基于流量均衡的读写控制算法。经测试应用表明,该DDR控制器具有更好的可靠性、有效性和适用性。For the deficiencies of the existing DDR controller to read and write data in DDR memory, a DDR controller in high-speed data acquisition card based on FPGA is designed. A data processing method based on the assembly of multiple payload packets and the idea of transferred meaning, and the reading and writing control algorithm based on balanced flux is proposed. The test applications show that the DDR controller has better reliability, va- lidity and applicability.

关 键 词：DDR控制器 数据采集 多包组装 转义 读写均衡 

分 类 号：TN919.5[电子电信—通信与信息系统]