民用机载电子硬件的SEU效应FPGA仿真测试研究  

FPGA Simulating Test for the SEU Effect of Civilian Airborne Electronic Hardware

作　　者：薛茜男[1] 王鹏[1] 田毅[1] 白杰[1] 

机构地区：[1]中国民航大学适航审定技术与管理研究中心,民用航空器适航与维修重点实验室,天津300300

出　　处：《电子器件》2013年第1期68-72,共5页Chinese Journal of Electron Devices

基　　金：中国民航大学科研启动基金项目(2012QD26X);航空科学基金项目(20128067003);中央高校基本科研业务费项目(ZXH2009A001)

摘　　要：针对民用机载电子硬件的现场可编程门阵列(FPGA)芯片高使用频率和长时间运行的特点,以及联邦航空管理局(FAA)等提出的审查条例对单粒子翻转效应(SEU)的防护要求,介绍了民用机载电子硬件的SEU效应评估研究的必要性。并且从民用机载电子硬件主流的三模冗余容错电路入手,设计了SEU效应仿真测试电路。将冗余系统与多时钟沿触发相结合,提高了系统的检错能力。对冗余系统进行仿真SEU故障注入,通过与参照单元的比较,可对SEU效应引起的失效的发生进行仿真测试。For the field programmable gate array chips of civilian airborne electronic hardware with the high frequency and long run time, a few of International Civil Aviation Organization such as FAA proposed the handbook for the protection requirements on the Single Event Effects. This paper reported the need for assessment studies on the SEU （Single Event Upset ）effect of civilian airborne electronic hardware. Besides, a single event effects simulating test circuit was designed with the redundant system and multi-clock edge trigger. The simulating results show that the error detection capability by the designed circuit was increased. Through the simulating fault injection of single event upset on the redundant system and comparing with the reference unit, the failure caused by the single event effects could be simulating test.

关 键 词：民用航空 SEU 检错电路 多时钟沿 FPGA 

分 类 号：TN710-34[电子电信—电路与系统]