LDPC码译码器的设计与实现  

Design and Implementation of LDPC Code Decoder

作　　者：朱联祥[1] 何凯[1] 何圆圆[1] 古昌金[1] 

机构地区：[1]重庆邮电大学信号与信息处理重庆市重点实验室,重庆400065

出　　处：《电视技术》2013年第7期120-122,共3页Video Engineering

摘　　要：由于传统的LLR BP译码算法不易于FPGA实现,为了降低实现复杂度,采用一种改进的LLR BP译码实现方法,设计了一种码长为40、码率为0.5的规则LDPC码译码器,并完成了FPGA仿真实现。仿真和综合的结果表明,所设计的译码器吞吐量达到15.68 Mbit/s,且译码器的资源消耗适中。Because the traditional LLR BP decoding algorithm is not easy to be implemented with FPGA, a modified LLR BP decoding implementation method is proposed in order to reduce the complexity of implementation, and a kind of LDPC code decoder is designed and implemented in FPGA for the regular LDPC code,whose code length is 40 and code rate is 0.5. The simulation and synthesis results show that the decoder throughput reached 15.68 Mbit/s, and the resource consumption of decoder is moderate.

关 键 词：LDPC码 LLR BP 译码器 FPGA 

分 类 号：TN911.22[电子电信—通信与信息系统]