65nm工艺下基于PCI Express2.0协议的物理编码子层设计  

An Efficient Physical Coding Sublayer for PCI Express2.0 in 65nm CMOS

作　　者：刘奇浩[1,2] 翁惠辉[1] 张锋[2] 赵建中[2] 吕俊盛[2] 李优[2] 

机构地区：[1]长江大学电子信息学院,湖北荆州34023 [2]中国科学院微电子研究所,北京100029

出　　处：《中国集成电路》2013年第3期40-45,共6页China lntegrated Circuit

基　　金：国家"八六三"计划项目(2011AA010403)

摘　　要：设计了一种应用于PCI Express2.0协议的物理编码子层,可以与物理媒介连接子层共同构成独立的物理层芯片。本文从面积与功耗方面对8b10b编解码的两种实现方法进行比较;并设计了复位控制器、头字符检测电路、时钟补偿弹性缓冲器、内建自测试等电路。全部电路在SMIC 65nm CMOS工艺下综合,SS工艺角、工作频率500MHz条件下芯片面积为5500μm2,动态功耗为2.74mW。An efficient Physical Coding Sublayer operating at 500MHz has been implemented based process for PCI Express 2.0, which was integrated into PHY with physical media attachment layer. on 65 nm CMOS Two methods of 8bl0b codec were compared in area and dynamic power consumption. A reset controller for initialization, elastic buffer for clock compensation and built-in-self-test circuit were employed. The circuit was synthesized at the speed of 500MHz in SS with an area of about 5500 μ m2 and the dynamic power consumption of 2.74 mW operating in FF.

关 键 词：PCI Express2.0 物理编码子层 8b10b编解码 弹性缓冲器 

分 类 号：TN919.31[电子电信—通信与信息系统]