采用多级噪声抵消技术的CMOS全差分LNA设计  

CMOS fully differential LNA design with multi-grade noise cancellation technology

作　　者：姚春琦[1] 毛陆虹[1] 张世林[1] 谢生[1] 

机构地区：[1]天津大学电子信息工程学院,天津300072

出　　处：《电路与系统学报》2013年第1期90-94,101,共6页Journal of Circuits and Systems

摘　　要：设计了一种用于2.4GHz RFID单芯片阅读器的CMOS低噪声放大器(LNA)。该设计采用全差分共源共栅结构和新颖的多级噪声抵消技术,不仅减小了电路的噪声而且增加了系统的线性度。芯片采用标准UMC 0.18um CMOS工艺,工作电压为1.2V时,消耗电流小于8mA,后仿真结果表明2.4GHz时,芯片达到1.69dB噪声系数,大于14.25dB功率增益以及-1.1dBm的输入三阶截点(IIP3)。设计满足单芯片阅读器低噪声,低功耗和高线性度的要求。A 2.4 GHz CMOS low noise amplifier （LNA） is presented for the use of single-chip RFID reader. The design uses a fully differential cascode structure and a novel multi-stages noise cancellation technology, not only reducing noise but also increasing linearity of the system. The chip uses a standard UMC 0.18urn CMOS process, when working at 1.2V, the current consumption is less than 8mA, post-simulation result shows that： working at 2.4GHz, we get 1.69dE noise figure, larger than 14.25dB power gain and -1.1dBm input third-order intercept point （IIP3）. This design meets the requirements of single-chip reader： low noise, low power consumption and high linearity.

关 键 词：低噪声放大器 噪声消除技术 线性度改善技术 CMOS射频集成电路 

分 类 号：TN431.1[电子电信—微电子学与固体电子学]