0.35μm CMOS多晶硅栅刻蚀工艺研究  

Study of Poly-silicon Gate Etching Process Based on 0.35μm CMOS

作　　者：公衍刚[1] 梁永杰[1] 刘存生[1] 孙有民[1] 

机构地区：[1]西安微电子技术研究所,陕西西安710054

出　　处：《微电子学与计算机》2013年第4期156-159,共4页Microelectronics & Computer

摘　　要：本文主要研究0.35μm CMOS多晶硅栅刻蚀工艺中"硅LOSS"及"T腰"问题的形成机理.在不改变产品工艺流程的前提下,对多晶硅栅刻蚀工艺进行优化,提出"两步ME法"优化了刻蚀形貌,改善了硅LOSS、T腰的问题.满足0.35μm CMOS多晶形貌及工艺要求,具有一定的理论指导和实际意义.Poly-silicon gate etching process based on the 0. 35μm CMOS was studied in detail, and the formation mechanism of silicon loss and profile T on the sidewall was investigated in this paper. Moreover, the paper optimized the etch process and finally found the ＂two procedures of Main Etch＂ method to solve the problems of silicon loss and profile T, by not changing other process conditions of CMOS. The result is accorded with the 0. 3Stem CMOS process specification very well. The paper has the theoretical direction and practical value.

关 键 词：多晶刻蚀 0 35μm CMOS 硅LOSS T腰 ME 

分 类 号：TN405.98[电子电信—微电子学与固体电子学]