TD-LTE系统中基于FPGA的解调与解扰的仿真和实现  

Realization and simulation of demodulation and descramble in TD-LTE system based on FPGA

作　　者：何登平[1] 江曹勇[1] 李小文[1] 步清明[1] 

机构地区：[1]重庆邮电大学重庆市移动通信技术重点实验室,重庆400065

出　　处：《电子技术应用》2013年第5期22-24,28,共4页Application of Electronic Technique

基　　金：国家科技重大专项项目(2011ZX03001-002)

摘　　要：基于FPGA实现TD-LTE系统中的解调与解扰。包括解调与解扰的介绍、max-log-map算法的介绍、方案的构成、FPGA实现流程以及实现结果分析。在Virtex-6芯片上进行了仿真、综合、板级验证。实现结果表明,该解调与解扰算法应用到TD-LTE射频一致性测试仪表中具有良好的高效性和可靠性。This paper mainly realizes demodulation and descramble in TD-LTE system. It includes the introduction of demodu- lation and descramble, max-log-map algorithm, projects form, the process of FPGA implementation and the results analysis. Then it finishes simulation, synthesis and verification of board on Virtex-6.The results show that this algorithm of demodulation and de-scramble have a high effectively and good reliability to TD-LTE RF conformance testing instrument.

关 键 词：FPGA实现 TD—LTE系统 解调与解扰 MAX-LOG-MAP算法 

分 类 号：TN929.5[电子电信—通信与信息系统]