FPGA实现Σ-Δ式DAC及其性能分析  

Synthesized Delta-Sigma DAC by FPGA and Its Performance

作　　者：葛俊杰[1] 刘旭东[1] 刘爱东[2] 

机构地区：[1]烟台职业学院信息工程系,山东烟台264670 [2]海军航空工程学院兵器科学与技术系,山东烟台264001

出　　处：《武汉理工大学学报（信息与管理工程版）》2013年第2期187-190,共4页Journal of Wuhan University of Technology：Information & Management Engineering

基　　金：航空科研基金资助项目(20085584010);山东省高等学校科技计划基金资助项目(J12LN74)

摘　　要：通过对Δ调制信号特点的分析提出了累加实现Σ-Δ式DAC的数学模型,利用FPGA实现了该数学模型,通过增加两个冗余位简化了电路设计,给出了Verilog实现程序,定量分析了其准确度、抖动性和快速响应特性,并据此给出了滤波器设计方案和应用特点。The characteristics of △ modulation signal were analyzed, and then the mathematical model of accumulation ∑ - △ DAC was proposed. The FPGA was applied to the realization of the mathematical model. The design on electric circuit was simplified by increasing 2 redundancies. Verilog execution routine was given. Its accuracy,jitter and fast response characteristics were quantitatively analyzed. Based on the analysis, the filter design plan and application characteristics were demonstrated.

关 键 词：FPGA Σ-Δ调制 D A转换器 性能分析 滤波器 

分 类 号：TP335.1[自动化与计算机技术—计算机系统结构] TP274.2[自动化与计算机技术—计算机科学与技术]