An improved technology for eliminating nondeterministic latency in the L1 trigger system  

作　　者：DU Zhongwei SU Hong KONG Jie ZHAO Xingwen QIAN Yi 

机构地区：[1]State Key Laboratory of Particle Detection & Electronics,University of Science and technology of China [2]Institute of Modern Physics,Chinese Academy of Sciences

出　　处：《Nuclear Science and Techniques》2013年第2期47-52,共6页核技术（英文）

基　　金：Supported by the Important Direction Project of the CAS Knowledge Innovation Program(No.KJCX2-YW-N27);the National Natural Science Foundation of China(No.11079045)

摘　　要：Gamma Ray Array Detector(GRAD) is one of external target facility subsystems in the Cooling Storage Ring on the Heavy Ion Research Facility at Lanzhou(HIRFL-CSR).The trigger subsystem of GRAD is required to make a fast L1 trigger decision with a fixed latency for the data acquisition.Because the hit signals from the detector are asynchronous with the local clock of the trigger system,a nondeterministic latency(the value changes between zero and one clock period) is generated when the synchronous receivers of the conventional trigger system process the hit signals.In this paper,an improved trigger logic based on a field-programmable gate array is developed,and comprised of zero-delay broadening circuits as receivers and an improved adding circuit designed for the new receivers.Software simulation and experimental measurement have been conducted.Comparison with the conventional trigger logic,the improved trigger logic has the advantage of eliminating the nondeterministic latency and reducing the total processing latency.Gamma Ray Array Detector （GRAD） is one of external target facility subsystems in the Cooling Storage Ring on the Heavy Ion Research Facility at Lanzhou （HIRFL-CSR）. The trigger subsystem of GRAD is required to make a fast L1 trigger decision with a fixed latency for the data acquisition. Because the hit signals from the detector are asynchronous with the local clock of the trigger system, a nondeterministic latency （the value changes between zero and one clock period） is generated when the synchronous receivers of the conventional trigger system process the hit signals. In this paper, an improved trigger logic based on a field-programmable gate array is developed, and comprised of zero-delay broadening circuits as receivers and an improved adding circuit designed for the new receivers. Software simulation and experimental measurement have been conducted. Comparison with the conventional trigger logic, the improved trigger logic has the advantage of eliminating the nondeterministic latency and reducing the total processing latency.

关 键 词：触发系统 延迟 不确定性 HIRFL-CSR 现场可编程门阵列 重离子研究装置 技术 时钟周期 

分 类 号：O572.212[理学—粒子物理与原子核物理]